The invention relates to an integrated circuit, comprising a memory having cells arranged in rows and columns, each cell comprising a transistor connected between two bit lines and having a current channel, a control gate and a charge-storage region therebetween, neighboring cells in a same row having a bit line contact in common, and control gates of transistors in a row being connected to a same word line.
An integrated circuit of this kind is known, for instance from the U.S. Pat. No. 4,281,397. The disclosed circuit comprises a memory matrix, in a first row whereof a first pair of cells in neighboring columns have a single bit line contact in common with a second row adjacent to the first row. The transistor has three control terminals: a source and a drain, both connected to consecutive bit lines, and a control gate, connected to a word line. In addition the transistor has a charge-storage region formed by a floating gate, capacitively coupled to the control gate. Programming of said transistor is accomplished by applying the programming voltage between the source and the drain while holding the control gate at the high programming voltage. A current through the transistor thereby causes tunneling of some charge carriers towards the floating gate. The charge trapped at the floating gate determines the threshold voltage of the transistor, indicative of its logical state.
The multiple use of bit line contacts leads to a dense memory matrix. A similar architecture with multiple use of bit line contacts could also be applied to a memory comprising transistors, each whereof has, in addition to the control terminals mentioned above, a separate injector. An example of such a transistor is described in U.S. Pat. No. 4,334,292. This latter transistor has in a substrate of a first conductivity type, drain- and source-regions of a second conductivity type, the injector comprising a part isolated from and extending opposite the charge-storage region, which also is isolated from said substrate. However, utilizing the known architecture in a straightforward way, would lead to a memory matrix wherein the number of control lines and contacts would increase considerably, for each injector should be (as it is disclosed) connected to a respective control line.